Reduced leakage memory cells

ABSTRACT

Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

RELATED APPLICATION

This is a divisional of U.S. patent application Ser. No. 11/524,343,filed Sep. 20, 2006, which is incorporated herein by reference in itsentirety.

TECHNICAL FIELD

The information disclosed herein relates generally to embodiments ofsemiconductor devices, including memory cells.

BACKGROUND

The semiconductor device industry has a market-driven need to reduce thesize of devices used, for example, in dynamic random access memories(DRAMs) that are found in computers and mobile communications systems.Currently, the industry relies on the ability to reduce or scale thedimensions of its basic devices to increase device density. Thisincludes scaling the channel length of the metal oxide semiconductorfield effect transistor (MOSFET). Increased channel scaling of theMOSFET can lower the channel resistance. Consequently, channel leakagecurrents may increase. This relationship has made the present MOSFETchannel design less useful for providing increasingly smaller memorycells, and thus, there is a need to find other mechanisms to generatereduced cell geometry.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsdescribe substantially similar components throughout the several views.Like numerals having different letter suffixes represent differentinstances of substantially similar components. The drawings illustrategenerally, by way of example, but not by way of limitation, variousembodiments discussed in this document.

FIG. 1A-C are cross-sections illustrating nanorod formation according tovarious embodiments of the invention.

FIG. 1D is a perspective view of nanorods according to variousembodiments of the invention.

FIG. 2A-B are cross-sections illustrating a MOSFET according to variousembodiments of the invention.

FIG. 3 is a surface view illustrating a MOSFET according to variousembodiments of the invention.

FIG. 4 is a cross-section illustrating a memory cell according tovarious embodiments of the invention.

FIG. 5 is block diagram of a memory device according to variousembodiments of the invention

FIG. 6 illustrates a semiconductor wafer according to variousembodiments of the invention.

FIG. 7 illustrates a circuit module according to various embodiments ofthe invention.

FIG. 8 is a block diagram illustrating a circuit module as a memorymodule according to various embodiments of the invention.

FIG. 9 is a block diagram illustrating an electronic system according tovarious embodiments of the invention.

FIG. 10 is a block diagram illustrating an electronic system as a memorysystem according to various embodiments of the invention.

FIG. 11 is a block diagram illustrating an electronic system as acomputer system according to various embodiments of the invention.

DETAILED DESCRIPTION

One approach to increasing the on-chip storage capacity of asemiconductor is to increase the number of capacitor cells per unitarea, which generally means reducing the overall size of the capacitor.However, reducing capacitor size may result in a lower capacitance percell. If the lower cell capacitance means more capacitive elements areneeded to maintain or improve upon a performance characteristic, such asthe ability to maintain a storage charge over time, then any gain incapacitor density may be offset. The double-sided capacitor provides oneuseful device structure for increasing capacitance without acommensurate increase in area. A double-sided capacitor may be scaledsmaller, for example, by increasing the dielectric constant of theinsulator material separating the capacitor plates.

A double-sided capacitor used for a DRAM memory cell is typicallycoupled to an access transistor located in close proximity. Forperformance reasons and to maximize cell density, the access transistorand the double-sided capacitor may be formed in a stackedcapacitor-transistor arrangement. A continued reduction in the size ofthe double-sided capacitor for such an arrangement then, may involvefurther reduction (or scaling) in the access transistor. In the case ofa MOSFET, scaling smaller typically means reducing the channel length aswell as channel width, which may lead to lower drain-source resistance(rds). Lower rds, may allow higher off-state leakage currents to flowbetween the drain and source. A lower rds may result from an increase inthe channel conduction due to a short channel effect such as draininduced barrier lowering (DIBL). Near the channel inversion threshold, apotential barrier may be formed between the source and the channelblocking drain current flow. The application of a drain voltage maydecrease the potential barrier height between the source and channel,increasing the drain current at near and below threshold. The draincurrent may therefore be due to the drain voltage as well as the gatevoltage, effectively reducing rds at near or below the inversionthreshold. A higher gate leakage current may also occur at shorterchannel lengths due to the higher gate electric fields. Many embodimentsof the invention may operate to reduce the leakage currents as thechannel length is reduced.

The bulk (or native) band gap energy of a semiconductor material is theenergy separation between the conduction and valance bands having athree dimensional continuum of energy states. A semiconductor materialwith a three dimensional continuum of energy states does not, generally,exhibit substantial quantum size effects such as discrete energy levels,spin-orbit splitting of heavy and light hole bands and changes in bandgap separation. Quantum size effects may be introduced by altering acrystal's dimensions. A change in the physical dimensions of a singlecrystal semiconductor material does not generally change the bulk bandgap energy of the material, if all three crystal dimensions aresufficiently large. Conversely, reducing the size of a semiconductormaterial may cause the band gap energy of the material to increase orshift to higher energy, if at least one of the three crystal dimensionsis made sufficiently small. For example, a rod shaped from semiconductormaterial may cause the energy band gap of the material to increase aboveits bulk band gap energy state as the diameter or the length of the rodis reduced. The change in the energy band gap of a rod-shaped materialcaused by its small dimensions may be exploited. A rod with a diameteron the order of a nanometer may be termed a “nanorod”.

In many embodiments, vertical transistor channels are formed using oneor more semiconductor nanorods oriented substantially perpendicular to asurface of a substrate. In some cases, the channels comprise a nanorodshape. In some cases, the channel region is formed using multiplenanorods. And in some cases, a nanorod includes the channel region.

Nanorods offer alternatives to the designers of MOSFET-based devicessince the geometry can be used to alter the electronic properties of theMOSFET channel using quantum size effects. As the diameter of thenanorod channel is reduced, a shift in the density of states, from athree-dimensional continuum of states to a two-dimensional density ofstates in the channel region may occur. Consequently, the electron andhole effective mass may be reduced and the band gap energy of thesemiconductor material may increase in the channel. The lower effectivemasses of the charge carriers may provide improved carrier transportproperties such as higher carrier mobilities. A MOSFET channel with ahigher band gap energy may provide a low leakage current between sourceand drain regions, a lower gate-channel leakage current and a fasterswitching speed.

A common MOSFET channel material is single crystal silicon. Silicon is amaterial where the electronic band gap increases as the physical size ofthe crystal decreases. For a MOSFET with a silicon vertical electronchannel shaped as a nanorod, or a silicon vertical electron channelformed with multiple nanorods, reducing the diameter of the nanorod, forexample from 13 nm to 7 nm, increases the band gap energy at roomtemperature from its bulk (or native) band gap energy of 1.12 eV to 3.5eV. Additional energy band gap separation may be possible by decreasingthe nanorod diameter ever further. Lowering the surface state density ofthe channel along the side of the nanorod using a dielectric or asemiconductor with a band gap energy exceeding the higher energy of thenanorod, may also increase the band gap separation. Increasing the bandgap separation may reduce DIBL and other short channel effects,including band-to-band tunneling induced off-state leakage.

FIG. 1A is a cross-section illustrating nanorod formation according tovarious embodiments of the invention. In many embodiments, substrate101A comprises a silicon substrate, but substrate materials other thansilicon, such as silicon germanium, may be used. In some embodiments,substrate 101A may comprise a wafer, such as a silicon wafer. In variousembodiments, substrate 101A may comprise a silicon on sapphire or asilicon on insulator. The substrate 101A may also comprise anisoelectronic material such as isoelectronic silicon. Variousembodiments include the substrate 101A with (001), (011) and (111)oriented crystal surfaces. In some embodiments, the substrate 101A maybe cut and/or polished off-axis with an angle ranging from 0.5° to 15°relative to the on-axis cut surface normal (shown as Y).

The impurity and/or electrical carrier concentration in layer 102A maybe adjusted to obtain the desired layer conductivity. For example, layer102A may be a doped to provide an n-type conductivity. In someembodiments, the layer 102A may have p-type conductivity. In variousembodiments, the layer 102A may be a substantially unintentionally doped(or undoped) layer. In various embodiments, the layer 102A may be of thesame conductivity type as the substrate 101A. In some embodiments, thelayer 102A has substantially the same electrical impurity concentrationas the substrate 101A. In various embodiments, layer 102A is formed fromthe substrate 101A. In some embodiments, layer 102A may comprise aportion of the substrate 101A. In various embodiments, layer 102A maycomprise an epitaxially grown or deposited film. In some embodiments,the impurity concentration and conductivity type of the layer 102A maybe adjusted using ion implantation to achieve the desired electricalconcentration.

The layer 103A may be formed on layer 102A and, in some embodiments, maybe formed from layer 102A. The layer 103A may be formed using anepitaxial process or a deposition process. Layer 103A and layer 102A maybe of the same or of a different conductivity type. In variousembodiments, layer 103A is a substantially unintentionally doped layer.In some embodiments, layer 103A is a doped layer having an impurityconcentration of less than 1×1017 cm-3. Examples of n-type impuritiesinclude P, As, and Sb. Examples of p-type impurities include B, Ga andIn. In some embodiments, layer 103A may have an electrically activeconcentration of less than 1×1017 cm-3. In various embodiments, theimpurity and/or electrically active concentration is graded in adirection substantially perpendicular to the surface normal. In variousembodiments, the impurity and/or electrically active concentration isgraded in a direction substantially parallel to the surface normal. Insome embodiments, the impurity concentration and conductivity type oflayer 103A may be adjusted using ion implantation to provide aparticular electrical concentration. In some embodiments, layer 103A hassubstantially the same conductivity type as the substrate 101A. Invarious embodiments, layer 103A is formed from the substrate 101A. Insome embodiments, layer 103A may form a portion of the substrate 101A.In various embodiments, layers 103A, 102A and substrate 101A may beformed from a single wafer such as a silicon wafer.

As shown in FIG. 1A, layer 105A may be formed on the surface of thelayer 103A as a mask layer. Layer 105A may be formed in the shape of aline, square, circle or other geometry as desired. Layer 105A may beformed of any number of patternable materials such a photoresist, ametal, or a dielectric adaptable to various lithography processes.Spacers 104A may be formed adjacent to layer 105A using a suitable etchresistant material. In some embodiments, layer 104A may comprise,without limitation, a semiconductor material such as SiGe, SiC andSiGeC, a dielectric such as silicon nitride, an oxynitride and SiO2, apolymer such as a photoresist, a block polymer such as diblock copolymerblends of polystyrene and polymethylmethacrylate, a metal such as W, MO,Ta and Al, or some combination of one or more layers of semiconductors,polymers, block polymers, dielectrics and metals. In variousembodiments, the spacers 104A may be formed as a self-assembled layer ina shape of an annular ring. In some embodiments, the spacers may beformed as a self-assembled layer with an island-like profile. In variousembodiment, the spacers 104A may be formed as a self-assembled layerforming a circular shaped hole. In some embodiment, the spacers 104A maybe formed by a self-assembled layer process without the layer 105A.

FIG. 1B is a cross-section illustrating nanorod formation according tovarious embodiments of the invention. Here, the layer 105A of FIG. 1A isshown removed, leaving spacers 104B substantially unchanged on layer103B. At this point, layers 102B and/or 103B may be further processed asdesired using for example, diffusion, implantation, and anneal processesto adjust the electrical and mechanical properties of the respectivelayers between the spacers 104B. In some embodiments, 102B and/or 103Bmay be further processed to adjust the electrical and mechanicalproperties of a portion of the respective layers directly under thespacers 104B using the spacers as a mask. In various embodiments, theelectrical properties of the layer 102B may be adjusted to provide aconductive region adjacent to the spacers 104B. In various embodiments,the electrical properties of the layer 102B may be adjusted to form oneor more shared doped regions extending, at least in part, laterallyunder the spacers 104B. In some embodiments, the electrical propertiesof the layer 102B may be adjusted to form a region contacting a dopedregion.

FIG. 1C is a cross-section illustrating nanorod formation according tovarious embodiments of the invention. Here, layer 103C and a portion oflayer 102C are shown removed between the spacers 104C forming a verticalnanorod structure 110C. The material between the spacers 104C may beremoved using an etch process, such as a wet chemical etch, a gas etchsuch as a plasma etch, and other suitable processes. In variousembodiments, the depth of the etch may be less than 1 □m. Layer 103C ofthe vertical nanorod structure 110C forms the channel region and layer102C forms a shared doped drain/source region of a transistor. In someembodiments, the channel portion of the vertical structure may be lessthan 0.5 □m.

The nanorods 110C may be formed as a pillars or columns and may have alateral cross-section shaped substantially in the form of a diskpresenting a vertical rod-like structure as illustrated in FIG. 1D.

FIG. 1D illustrates nanorods 110D formed according to variousembodiments of the invention. The diameter of the layer 103D below thespacers 104C may range from about 0.5 nm to about 15 nm. In someembodiments, a diameter of the 103D layer below the spacers 104D mayrange from about 1 nm to about 10 nm. In general, the diameter may bechosen according to the desired energy band shift. In variousembodiments, the layer 103D between the spacers 102D may be partiallyremoved. In some embodiments, layers 102D, 103D and a portion ofsubstrate material 101D may be removed between the spacers 104D suchthat there is no shared doped region using layer 102D without furtherprocessing (not shown).

In some embodiments, layers 102D and 103D are formed from the substratematerial 101D. For example, layer 102D and 103D may be a portion of thesubstrate material 101D that is a semiconductor wafer. In variousembodiments, substrate 101D is a single crystal silicon wafer. In someembodiments, layers 102D, 103D and 101D comprise silicon layers. Invarious embodiments, layer 102D and 103D may comprise SiGe layers. Insome embodiments, layer 102D may be a SiGe layer and 103D may comprise asilicon layer. In various embodiments, layer 102D may comprise a siliconlayer and 103D a SiGe layer. In some embodiments, layer 102D and/orlayer 103D may comprise a SiC layer or a SiGeC layer.

FIG. 2A is cross-section illustrating a MOS transistor according tovarious embodiments of the invention. Here, the vertical nanorod 210A isfirst formed, then a gate dielectric 206A is formed in contact with thechannel region 203A of the vertical nanorods. Insulator 207A may beformed between the nanorods over layer 202A. An optional field insulatormay be further formed between the nanorods (not shown). The gatedielectric 206A may be formed along the sides of the nanorods 210Asurrounding or enclosing the channel region. In some embodiments, theinsulator 207A and the gate dielectric 206A are formed of the samedielectric material. In various embodiments, the insulator 207A and thegate dielectric 206A may be different materials. Examples of gatedielectric materials include, without limitation, SiO2, SiN, andnitrides and oxidynitrides formed with Si, Mo, W, Ta, Hf, and Al. Insome embodiments the gate dielectric may comprise a compositemulti-layer dielectric. The thickness of the gate dielectric 206A mayrange from about 2 nm to about 20 nm, depending on the gate dielectricmaterial and related properties such as a dielectric constant. In someembodiments, the insulator 207A and the gate dielectric 206A may beformed with the same thickness or with different thicknesses.

FIG. 2B is cross-section illustrating a MOS transistor according tovarious embodiments of the invention. Here, two access transistors 200Bare shown separated by an isolation region 212B formed on the substrate201B. The isolation region 212B may be a shallow trench isolation regionformed in the shared drain/source region 202B to electrically isolatethe access transistors 200B. Isolation region 212B may be an etchedregion filled with a dielectric material such as vapor deposited SiO2.In some embodiments, the isolation region 212B may be formed in aportion of the substrate 201B. The access transistors include thevertical nanorods 210B with a drain/source region 211B at one end of thenanorod in contact with channel region 203B, and a shared drain/sourceregion 202B at the second end in contact with the channel region. Insome embodiments, an isolation region may used to electrically isolate aplurality of vertical nanorods configured in parallel to form a verticalchannel transistor. In some embodiments, the length of the verticalchannel region 203B may be less than 250 nm. In various embodiments, thelength of the vertical channel region 203B may be between about 20 nmand about 150 nm.

The gate conductor 208B may be formed over the gate dielectric 206B thatsurrounds the nanorods in the channel region 203B. The gate region maybe formed as a shared conductive gate region by filling-in the areabetween the nanorods 210B with a suitable conductive material. In someembodiments, the gate region may be formed such that there is no sharedgate region. Examples of conductive gate region materials include, butare not limited to, polysilicon, metals such as Al, W, Mo and Ta,binaries such as TiN and TaN, metal silicides such as WSix, NiSi, CoSixand TiSix, a dacecamine, and combinations of layers of conductivematerial. Field insulator 209B may be formed overlaying gate conductor208B and may comprise any suitable insulator, including, withoutlimitation, SiO2, SiN, and oxynitride-based dielectrics containing Si,Al, W, Ta, Ti, and Mo.

Drain/source region 211B and shared source/drain region 202B may beconfigured to be in electrical contact using the vertical channel region203B of the nanorods such that no current flows across the channelregion with zero gate bias voltage applied to gate conductor 208B.Drain/source region 211B may be formed by epitaxial growth, ionimplantation, and deposition processes. In some embodiments, thedrain/source region 211B may be formed as a shared region. In variousembodiments, drain/source region 211B may comprise silicon, dopedpolysilicon, SiC, SiGe or SiGeC. A substantially planar surface may beobtained for the field dielectric 209B and drain source region 211Busing a chemical mechanical process as are known to those of ordinaryskill in the art. In various embodiments, a conductive region overlayinginsulator 209B and the drain/source region 211B may be formed to couplethe nanorods 210B (not shown).

FIG. 3 is a surface view of a MOS transistor according to variousembodiments of the invention. Here, the access transistor 300 is shownwith nine nanorods 310 and an isolation region 312, but may include moreor less nanorods. The vertical channel region 203B of FIG. 2B coupled tothe drain/source region 302 form a composite of parallel channels, whichmay be electrically coupled to a capacitor at 311 (not shown). In someembodiments, the isolation region 312 may be used electrically isolate aplurality of vertical channel regions. In various embodiments, theisolation region 312 may be used to electrically isolate the verticalchannel regions of an access transistor 300 from the vertical channelregions of an adjacent access transistor 300. In some embodiments, theisolation region 312 may be used to isolate a capacitor coupled to theaccess transistor 300 from adjacent capacitor cells (not shown). As showby way of example in FIG. 3, but not by limitation, a shared annulargate arrangement of nine nanorods 310 may be formed with acenter-to-center spacing of 24 nm using vertical nanorod channels (notshown) having about a 10 nm diameter, a gate dielectric 306 with about a2 nm radial thickness and gate conductor 308 with about a 5 nm radialthickness. Various embodiments include a gate dielectric thicknessesranging from about 2 nm to about 20 nm, channel region diameters rangingfrom about 0.5 nm to about 15 nm, and conductive gate region thicknessesranging from about 3 nm to about 10 nm. The number of parallel couplednanorods and/or channels formed as part of the access transistor, orother such transistor, may affect desired performance characteristics.In general, the number of vertical channels per surface area may bedetermined and adjusted according to specified design rules for aparticular manufacturing process.

FIG. 4 is a cross-section illustrating a memory cell according tovarious embodiments of the invention. Here, a DRAM cell 430 includes anaccess transistor 400 and double-sided capacitor 425, but any type ofcapacitor may be configured to be supported by and/or coupled to theaccess transistor. The double-sided capacitor stores electrical chargereceived from an input circuit (not shown) such that the chargeestablishes an electric field across the insulator 422 between capacitorplates 421 and 423. More information regarding fabrication of storagecell capacitors can be found in U.S. Pat. No. 6,030,847 entitled Methodfor Forming a Storage Capacitor Compatible with High Dielectric ConstantMaterial, and U.S. patent application Ser. No. 10/788,977 entitledSemiconductor Fabrication Using a Collar, both incorporated by referenceherein in their entirety.

In various embodiments, and as shown in FIG. 4, the n-type drain/sourceregion 411 of the access transistor 400 are in contact the nanorodchannels 403 and capacitor plate 421. The electric charge supporting theelectric field between capacitor plates 421 and 423 may place eachdrain/source region 411 in contact with capacitor plate 421 atsubstantially equal potential. In this case, charge may not flow thoughthe vertical channel region 403 of any nanorod 410 in the absence of abias potential on gate conductor 408. In some embodiments, the gateconductor 408 shared a conductor coupling the gate region of one or morenanorods. Thus, the gate conductor 408 may comprise multiple discretegate electrodes coupled using a conductor. The vertical channel 403 ofthe nanorods 410 may be sufficiently small in diameter so that theelectronic band gap energy of the material in the channel region 403 isgreater than in the non-channel regions, such as in the unetched portionof the n-type drain/source region 402 and the substrate layer 401. Invarious embodiments, the substrate 401, the n-type shared drain/sourceregion 402, the channel region 403 and/or the n-type drain/source region411 are formed from a material with the same lattice constant. In someembodiments, the substrate 401, the shared drain/source region 402, thechannel region 403 and/or the drain/source region 411 are formed ofsilicon. In various embodiments, the drain/source region 411 is madesufficiently large to eliminate quantum size effects, such as a higherenergy band gap shift. In some embodiments, the drains/source region 411may be shared drains/source region. In various embodiments, a portion ofthe shared drain/source region 402 is made sufficiently large toeliminate quantum size effects in that portion. In some embodiments, theshared drain/source region 402 is coupled to the ground plane 413 usingvia holes (not shown). In various embodiments, the shared source drainregion 402 may be used as a ground plane or a similar conductive region.In some embodiments, the substrate is coupled to the ground plane 413.In various embodiments, the substrate forms at least a part of aconductive plane such as a ground plane. In some embodiments, anelectrical isolation region (not shown) may be formed in the substratebetween the nanorods 410. In various embodiments, the substrate maycomprise an electrically non-conductive material such as a silicon waferwith a low carrier concentration. In some embodiments, the ground plane413 may comprise a series of ground planes. In various embodiments, theground plane 413 is formed as a plurality of conductors coupled to oneor more conductors, electrodes, circuit element, voltages and the like.

Charge placed on the capacitor 425 by a voltage signal transmitted byconductor from an input/output circuit (not shown), for example, may bestored during the access transistor's off-state since no further currentpath is provided. For the memory cell illustrated in FIG. 4, the chargemay be used to establish an electric field in the vertical directionbetween the capacitor plate 421 and the conductive ground plane 413. Aportion of the electric field may have a vertical potential gradientacross the channel region 403 of the nanorods 410 of the accesstransistor 400 between the source/drain regions 402, 411. In the absenceof voltage applied to the gate conductor 408, substantially no currentflows between drain/source regions 402, 411 (off-state).

Application of a voltage to the gate conductor 408 may establish anelectric field across gate dielectric 406 with field componentsperpendicular to the channel 403. A gate voltage in cooperation with thegate dielectric layer 406 may further generate a charge inversion layer(not shown) extending inward from the gate dielectric along the channel403 between drain/source regions 402, 411. The charge inversion layermay electrically couple the drain/source regions 402, 411 to form acurrent path there between. In some embodiments, the nanorods may have acircular cross-section and the electric field includes a radialpotential gradient. The formation of a current path between thecapacitor plate 421 in contact with the drain/source region 411 and theshared drain/source region 402 and/or substrate 401 and/or conductiveground plane 413, may allow the capacitor 425 to discharge through thechannel region, removing the capacitor's charge and the respectivevoltage and electric field.

In the transistor off-state, the energy band discontinuity (or energyband offset) between the capacitor plate 421 and the channel region 403may be larger with the nanorods 410 than for a transistor channel formedfrom the same material with a bulk band gap energy (e.g. withoutnanorods). This increased energy band offset may provide an increasedelectron barrier for blocking electrons thereby reducing the amount ofcharge escaping the capacitor plate 421 though the channel region 403.The increased energy band gap difference between the source/drain region402 and the channel region 403 may reduce DIBL by improving thesub-threshold ideality factor and sub-threshold voltage swing.Consequently, a reduction in the amount of charge leaking from thecapacitor 425 over time may occur through the access transistor 400. Asa result, the DRAM cell 430 may retain charge for longer times.

FIG. 5 is block diagram of a memory device 500 according to variousembodiments of the invention. The memory device 500 may include an arrayof memory cells 502, an address decoder 504, row access circuitry 506,column access circuitry 508, control circuitry 510, and an input/output(I/O) circuit 512. The memory cells 502 may comprise one or morecapacitor cells operatively coupled to the row access circuit 506 andthe column access circuit. The memory device 500 may be operably coupledto an external processor 514, or memory controller (not shown) toprovide access to the memory content. The memory device 500 is shown toreceive control signals from the processor 514, such as WE*, RAS* andCAS* signals. The memory device 500 may store data which is accessed viaI/O lines. It will be appreciated by those of ordinary skill in the artthat additional circuitry and control signals can be provided, and thatthe memory device of FIG. 5 has been simplified to help focus on, andnot obscure, various embodiments of the invention. Any of the memorycells, transistors, and associated circuitry may include an integratedcircuit structure and/or elements in accordance with various embodimentsof the invention. For example, the array of memory cells 502 may befabricated according to embodiments of the invention, so as to includeone or more nanorods, as shown in FIG. 1D

It should be understood that the above description of a memory device500 is intended to provide a general understanding of possible memorystructures, and is not a complete description of all the elements andfeatures of a specific type of memory, such as DRAM. Further, manyembodiments of the invention are equally applicable to any size and typeof memory circuit and are not intended to be limited to the DRAMdescribed above. Other alternative types of devices include SRAM (staticrandom access memory) and flash memories. Additionally, the DRAM couldcomprise a synchronous DRAM, commonly referred to as SGRAM (synchronousgraphics random access memory), SDRAM (synchronous DRAM), SDRAM II, andDDR SDRAM (double data rate SDRAM), as well as Synchlink™ or Rambus™DRAMs and other technologies.

FIG. 6 illustrates a semiconductor wafer 600 according to variousembodiments of the invention. As shown, a semiconductor die 610 may beproduced from a wafer 600. The semiconductor die 610 may be individuallypatterned on a substrate layer or wafer 600 that contains circuitry, orintegrated circuit devices, to perform a specific function. Thesemiconductor wafer 600 may contain a repeated pattern of suchsemiconductor dies 610 containing the same functionality. Thesemiconductor die 610 may be packaged in a protective casing (not shown)with leads extending therefrom (not shown), providing access to thecircuitry of the die for unilateral or bilateral communication andcontrol. The semiconductor die 610 may include an integrated circuitstructure or element in accordance with various embodiments of theinvention, including one or more nanorods, as shown in FIG. 1D.

FIG. 7 illustrates a circuit module 700 according to various embodimentof the invention. As shown in FIG. 7, two or more semiconductor dice 610may be combined, with or without a protective casing, into a circuitmodule 700 to enhance or extend the functionality of an individualsemiconductor die 610. The circuit module 700 may comprise a combinationof semiconductor dice 610 representing a variety of functions, or acombination of semiconductor dies 610 containing the same functionality.One or more semiconductor dice 610 of circuit module 700 may contain atleast one integrated circuit structure or element in accordance withembodiments of the invention, including one or more nanorods, as shownin FIG. 1D.

Some examples of a circuit module include memory modules, devicedrivers, power modules, communication modems, processor modules andapplication-specific modules, and may include multilayer, multichipmodules. The circuit module 700 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, a personal digital assistant, a network server suchas a file server or an application server, an automobile, an industrialcontrol system, an aircraft and others. The circuit module 700 may havea variety of leads 710 extending therefrom and coupled to thesemiconductor dice 610 providing unilateral or bilateral communicationand control.

FIG. 8 illustrates a circuit module as a memory module 800, according tovarious embodiment of the invention. A memory module 800 may includemultiple memory devices 810 contained on a support 815 (the numbergenerally depending upon the desired bus width and the desire for paritychecking). The memory module 800 may accept a command signal from anexternal controller (not shown) on a command link 820 and provide fordata input and data output on data links 830. The command link 820 anddata links 830 may be connected to leads 840 extending from the support815. The leads 840 are shown for conceptual purposes and are not limitedto the positions shown in FIG. 8. At least one of the memory devices 810may contain an integrated circuit structure or element in accordancewith embodiments of the invention, including one or more nanorods, asshown in FIG. 1D.

FIG. 9 illustrates a block diagram of an electronic system 900 accordingto various embodiment of the invention. FIG. 9 shows an electronicsystem 900 containing one or more circuit modules 700. The electronicsystem 900 may include a user interface 910 that provides a user of theelectronic system 900 with some form of control or observation of theresults generated by the electronic system 900. Some examples of a userinterface 910 include a keyboard, a pointing device, a monitor orprinter of a personal computer; a tuning dial, a display or speakers ofa radio; an ignition switch, gauges or gas pedal of an automobile; and acard reader, keypad, display or currency dispenser of an automatedteller machine, as well as other human-machine interfaces.

The user interface 910 may further include access ports provided toelectronic system 900. Access ports are used to connect an electronicsystem 900 to the more tangible user interface components previouslyprovided by way of example. One or more of the circuit modules 700 maycomprise a processor providing some form of manipulation, control ordirection of inputs from or outputs to the user interface 710, or ofother information either preprogrammed into, or otherwise provided to,the electronic system 900. As will be apparent from the lists ofexamples previously given, the electronic system 900 may be associatedwith certain mechanical components (not shown) in addition to thecircuit modules 700 and the user interface 910. It should be understoodthat the one or more circuit modules 700 in the electronic system 900can be replaced by a single integrated circuit. Furthermore, theelectronic system 900 may be a subcomponent of a larger electronicsystem. It should also be understood by those of ordinary skill in theart, after reading this disclosure that at least one of the memorymodules 700 may contain an integrated circuit structure or element inaccordance with embodiments of the invention, including one or morenanorods, as shown in FIG. 1D.

FIG. 10 illustrates a block diagram of an electronic system as a memorysystem 1000 according to various embodiment of the invention. A memorysystem 1000 may contain one or more memory modules 800 and a memorycontroller 1010. The memory modules 800 may each contain one or morememory devices 810. At least one of memory devices 810 may contain anintegrated circuit structure or element in accordance with embodimentsof the invention, including one or more nanorods, as shown in FIG. 1D.

The memory controller 1010 may provide and control a bidirectionalinterface between the memory system 1000 and an external system bus1020. In some embodiments, the memory controller 1010 may also containone or more nanorods, as shown in FIG. 1D. The memory system 1400 mayaccept a command signal from the external system bus 1020 and relay itto the one or more memory modules 800 on a command link 830. The memorysystem 1000 may provide data input and data output between the one ormore memory modules 800 and the external system bus 1020 on data links1040.

FIG. 11 illustrates a block diagram of an electronic system as acomputer system 1100 according to various embodiment of the invention. Acomputer system 1100 may contain a processor 1110 and a memory system1000 housed in a computer unit 1105. The computer system 1100 alsoserves as an example of an electronic system containing anotherelectronic system, i.e., memory system 1000, as a subcomponent. Thecomputer system 1100 optionally contains user interface components, suchas a keyboard 1120, a pointing device 1130, a monitor 1140, a printer1150 and a bulk storage device 1160. Other components associated withthe computer system 1100, such as modems, device driver cards,additional storage devices, etc. may also be included. The processor1110 and the memory system 1000 of the computer system 1100 can beincorporated on a single integrated circuit. Such single packageprocessing units may operate to reduce the communication time betweenthe processor and the memory circuit. The processor 1110 and the memorysystem 1000 may contain one or more nanorods, as shown in FIG. 1D. Insome embodiments, the printer 1150 or the bulk storage device 1160 maycontain an integrated circuit structure or element in accordance withembodiments of the invention, including one or more nanorods, as shownin FIG. 1D.

The above Detailed Description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments. These embodiments,which are also referred to herein as “examples,” are described in enoughdetail to enable those skilled in the art to practice the invention. Theembodiments may be combined, other embodiments may be utilized, orstructural, logical and electrical changes may be made without departingfrom the scope of the present invention. The Detailed Description is,therefore, not to be taken in a limiting sense, and the scope of thevarious embodiments is defined only by the appended claims and theirequivalents.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one. In this document, the term“or” is used to refer to a nonexclusive or, unless otherwise indicated.Furthermore, all publications, patents, and patent documents referred toin this document are incorporated by reference herein in their entirety,as though individually incorporated by reference. In the event ofinconsistent usages between this document and those documents soincorporated by reference, the usage in the incorporated reference(s)should be considered supplementary to that of this document; forirreconcilable inconsistencies, the usage in this document controls.

It is to be understood that the above description is intended to beillustrative, and not restrictive. For example, the above-describedembodiments (and/or aspects thereof) may be used in combination witheach other. Many other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionshould, therefore, be determined with reference to the appended claims,along with the full scope of equivalents to which such claims areentitled. In the appended claims, the terms “including” and “in which”are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, or process that includes elements in addition to those listedafter such a term in a claim are still deemed to fall within the scopeof that claim. Moreover, in the following claims, the terms “first,”“second,” and “third,” etc. are used merely as labels, and are notintended to impose numerical requirements on their objects.

The Abstract is provided to comply with 37 C.F.R. §1.72(b), whichrequires that it allow the reader to quickly ascertain the nature of thetechnical disclosure. It is submitted with the understanding that itwill not be used to interpret or limit the scope or meaning of theclaims. Also, in the above Detailed Description, various features may begrouped together to streamline the disclosure. This should not beinterpreted as intending that an unclaimed disclosed feature isessential to any claim. Rather, inventive subject matter may lie in lessthan all features of a particular disclosed embodiment. Thus, thefollowing claims are hereby incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment.

What is claimed is:
 1. A system comprising: a plurality of capacitivecells coupled to an input/output circuit, wherein some of the pluralityof capacitive cells include a capacitor coupled to an access transistorcomprising a vertical channel region configured to transfer chargebetween the capacitor and a conductive region based on a signalassociated with a processor, and wherein the vertical channel regioncomprises at least one nanorod configured to reduce a leakage currentbetween the capacitor and the conductive region using a band gap energydifference.
 2. The system of claim 1, wherein the at least one nanorodshares a gate region channel material.
 3. The system of claim 2, whereinthe gate region channel material includes at least one of a dielectricand a gate conductor.
 4. The system of claim 3, wherein the dielectricincludes a gate dielectric configured to support an inversion field inthe vertical channel region.
 5. The system of claim 1, wherein the atleast one nanorod is formed from at least one of a silicon substrate anda silicon wafer.
 6. The system of claim 1, wherein the capacitorincludes a double-sided capacitor.
 7. The system of claim 1, wherein theplurality of capacitive cells are configured to form a portion of amemory module.
 8. The system of claim 7, wherein the memory modulecomprises a DRAM module.
 9. The system of claim 1, wherein the at leastone nanorod includes a region with a band gap energy greater than 1.12eV.
 10. A method comprising: propagating charge through a predefinedvertical region in a semiconductor material according to a specifiedsignal, the vertical region coupled to an electrode associated with acapacitor; and blocking charge flow using the predefined verticalregion, wherein the semiconductor material has an electronic energy bandgap greater than its native band gap energy.
 11. The method of claim 10,wherein propagating includes propagating through at least one nanorod.12. The method of claim 10, wherein propagating includes propagatingcharge to discharge the capacitor.
 13. The method of claim 10, whereinblocking includes blocking charge associated with a leakage current. 14.The method of claim 10, wherein blocking includes selectively blockingusing the electronic energy band gap in combination with a bias fieldassociated with a gate potential.
 15. A method comprising: forming avertical channel transistor using a first semiconductor material and asecond semiconductor material, the first semiconductor materialincorporating a nanorod geometry to increase an electronic energy gap ofthe first semiconductor material, and the second semiconductor materialhaving a native electronic band gap energy less than the electronic bandgap energy of the first semiconductor material; and forming a gateregion enclosing a portion of first semiconductor material.
 16. Themethod of claim 15, wherein forming a vertical channel transistorincludes forming with a material that includes silicon.
 17. The methodof claim 15, wherein forming a vertical channel transistor using thefirst semiconductor material includes using a first semiconductormaterial with the same lattice constant as silicon.
 18. The method ofclaim 15, wherein forming a vertical transistor channel includes formingusing a self assembled layer.
 19. A method comprising: forming an accesstransistor comprising at least one vertical nanorod; forming a capacitorcell supported by the access transistor; and connecting the accesstransistor to the capacitor cell using a plurality of electrodes. 20.The method of claim 19, wherein forming an access transistor includesforming an annular gate structure.
 21. The method of claim 20, whereinforming an annular gate structure includes forming an annular gatedielectric and an annular gate electrode.
 22. The method of claim 19,wherein forming an access transistor includes forming a shareddrain/source region.
 23. The method of claim 19, wherein forming anaccess transistor includes removing material using a spacer layer. 24.The method of claim 23, wherein removing includes removing materialsupported by a substrate.
 25. The method of claim 23, wherein removingincludes removing at least one of a substrate material and a portion ofa semiconductor wafer.
 26. The method of claim 19, wherein forming anaccess transistor includes first forming the at least one verticalnanorod.
 27. The method of claim 19, wherein connecting the accesstransistor includes coupling the at least one nanorod to the capacitorcell using a capacitor plate.
 28. The method of claim 19, whereinconnecting the access transistor includes connecting the accesstransistor to the capacitor cell using a gate electrode.
 29. A methodcomprising: establishing a first electric field in a vertical electronchannel; establishing a second electric field in the vertical electronchannel to discharge a capacitor, wherein the vertical electron channelincludes a semiconductor material with a first band gap energy greaterthan silicon, and wherein the vertical electron channel is coupled to aregion of material with a second band gap energy lower than the firstband gap energy, and wherein at least one of the vertical electronchannel and the region of material have a lattice constant equal tosilicon.
 30. The method of claim 29, wherein establishing a firstelectric field includes establishing a charge on a capacitor plate. 31.The method of claim 30, wherein establishing a charge includesestablishing a charge on the capacitor plate associated with a doublesided capacitor.
 32. The method of claim 29, wherein establishing afirst electric field includes establishing a charge on a capacitorplate.
 33. The method of claim 29, wherein establishing a first electricfield includes establishing a first electric field with a verticalpotential gradient.
 34. The method of claim 29, wherein establishing asecond electric field includes discharging a capacitor associated with adynamic read only memory cell.
 35. The method of claim 29, whereinestablishing a second electric field includes establishing a secondelectric field with a radial potential gradient.
 36. A systemcomprising: a user interface coupled to a memory, the memory comprisinga plurality of capacitor cells, at least a portion of the capacitorcells including at least one access transistor, the access transistorcomprising at least one vertical channel shaped as a rod, wherein therod includes a first band gap energy region and a second band gap energyregion, the second band gap energy being lower than the first band gapenergy, and wherein the first band gap energy region and the second bandgap energy region cooperate to reduce a channel leakage current.
 37. Thesystem of claim 36, wherein the user interface is coupled to at leastone of a personal digital assistant, a cell phone, a television, acomputer and a network server.
 38. The system of claim 36, wherein theuser interface is configured to receive a signal associated with atleast one of a processor and a modem.
 39. The system of claim 36,wherein the user interface is configured to transmit a signal to atleast one of a processor, a display and a storage device.